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nuptsww木蟲 (小有名氣)
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[求助]
翻譯 一段 英文
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A typical FET is constructed with the basic components as shown in Fig. 1: source, drain and gate electrodes, a dielectric layer, and a semiconducting layer. OFETs adopt the architecture of the thin film transistor (TFT), which has proven its adaptability with low conductivity materials. The current flow between the drain and source electrodes is modulated by the applied gate voltage. When no gate voltage (VG) is applied, the drain current (ID) is very low if the semiconductor is not highly doped and the transistor is normally off. With an increase in the gate voltage, a layer of mobile charges can accumulate at the interface between the semiconductor and insulator. Then, the current is bigger due to the increased charge carriers and thus the transistor is in the on state. That is the operating principle of OFETs. Fig. 2 shows a typical output characteristic of an OFET, which corresponds to a device using copper phthalocyanine (CuPc) as the semiconductor, 500 nm thick SiO2 (Ci, 10 nF cm22) modified with an octadecyltrichlorosilane (OTS) selfassembled monolayer (SAM) as the gate insulator, a heavily doped n-type Si wafer as the gate electrode and gold as the source and drain electrodes. When the gate electrode is biased negatively, the transistor based on CuPc operates in the accumulation mode and the holes are the major charge carriers in the transistor channel. From the output, we can see that with the drain voltage increase, the device gradually enters the saturation regime from the linear regime where the drain current becomes independent of the drain bias. The current ID modulated by VG is approximately determined from the following equations: |
至尊木蟲 (小有名氣)
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供參考: 典型的FET(場(chǎng)效應(yīng)晶體管)由圖1所示的基本元件組成:源極、柵極、門電路元件,介質(zhì)層和半導(dǎo)體層。OFET采用薄膜晶體管結(jié)構(gòu),它與低傳導(dǎo)性材料的適應(yīng)性已得到證明。柵極和源極之間的電流由外加的門電壓調(diào)節(jié)。當(dāng)不加門電壓時(shí),如果半導(dǎo)體摻雜度不高且晶體管正常的話,柵電流很低。隨著門電壓增加,移動(dòng)的電荷會(huì)聚集在半導(dǎo)體和絕緣體之間的界面。由于電荷載體增加,電流變大,因此晶體管出于“開”的狀態(tài)。這就是OFET的工作原理。圖2 所示為OFET的輸出特性,它與用銅酞菁(CuPc)作為半導(dǎo)體的設(shè)備呼應(yīng),500毫米厚的二氧化硅(SiO2)根據(jù)自組合單層十八基三氯硅烷作為門絕緣體,摻雜度高的N型硅晶片作為門電極,黃金作為源極和柵極而修正。當(dāng)門電極陰極加偏壓,基于銅酞菁(CuPc)的晶體管在累加態(tài)下工作,晶體管信道內(nèi)的空穴是主要的電荷載體。我們從輸出可以看出,隨著柵電壓的增加,設(shè)備逐漸由線性區(qū)進(jìn)入飽和區(qū),在線性區(qū)內(nèi)刪電流與漏偏壓不相關(guān)。目前由可變?cè)鲆妫╒G)調(diào)節(jié)的儀器零點(diǎn)偏移(ID)近似地由下列方程確定.。 |
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