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幫朋友招聘——硅谷數(shù)模半導(dǎo)體有限公司
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職位 1：Sr. AE x 2名 工作職責(zé): 1. Work with marketing and development teams to define key product features during the product requirement definition; 2. Lead product validation and alpha customer roll out. Create validation plans, track issues from discovery to closure; 3. Develop system level workarounds, define errata, analyze defects and propose remedies; 4. Lesson and Learn management. 職位要求: 1. 7 years’ experience in semiconductor industry; 2. International work experience in a world class supplier or customer; 3. Experience in display or graphics preferred; 4. Experienced as a project lead preferred; 5. Strong system level debugging skill a must; 6. Able to read and analyze C-code, comfortable creating small programs in C-code; 7. Able to develop schematic and review PCB; 8. Strong communication skills, ability to articulate complex issues; 9. Good documentation skills 職位 2： Sr. Firmware Engineer x 1名 工作職責(zé): 1. Development/maintain the embedded firmware at product level (not just for chip companies); 2. Create a world class code base, set example for all release management process. 職位要求: 1. BS or above degree in EE, CE , CS or equivalent, 2. Fluent written and speaking English 3. Embedded firmware experience at product level. 4. Hardware skills(schematic read, oscilloscope, millimeter) are required. 5. Experience on 51 program. 6. IC company experience is preferred. 7. Be good at c/c++ , experienced to use code management tools(svn etc) 職位 3: Sr. Software Engineer x 1名 工作職責(zé): Develop/main tools and create pre-integrated solution in windows/android 職位要求: 1. Expert on C/C++, windows development(SDK/DDK); 2. Be good at visual c++, c#, visual basic etc.; 3. Experienced on android; 4. Experience for code management tools like svn etc. Digital Design Team: 職位 1：Sr. Digital IC Design Engineer x 1名 工作職責(zé): 1. Responsible for architecture definition according to product specifications; 2. Logic design & implementation by Verilog on module level, and chip integration; 3. Design synthesis, timing analysis, DFT and ATPG; 4. Work closely with backend engineer for chip tape-out; 5. Work closely with application engineer for chip bring-up, debug and solve problem. 職位要求: 1. Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science; 2. At least 2+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA.; 3. Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and PrimeTime.; 4. Familiar with cryptosystem such as RSA/AES is a big plus; 5. Familiar with FPGA prototyping is a big plus; 6. Familiar with mixed signal design is a big plus; 7. Good written and oral English communication skills. 如果有合適的同學(xué)，請(qǐng)把簡(jiǎn)歷發(fā)到121630448@qq.com 關(guān)于待遇和其他的福利問(wèn)題，請(qǐng)具體和他聯(lián)系。謝謝！ |
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